By K. Woodbridge (auth.), Yves I. Nissim, Emmanuel Rosencher (eds.)
In the sphere of good judgment circuits in microelectronics, the management of silicon is now strongly proven as a result of the fulfillment of its know-how. close to solidarity yield of 1 million transistor chips on very huge wafers (6 inches this day, eight inches the following day) are presently comprehensive in undefined. the prevalence of silicon over different fabric could be summarized as stick with: - The Si/Si0 interface is the main ideal passivating interface ever 2 acquired (less than 10" e y-I cm2 interface country density) - Silicon has a wide thermal conductivity in order that huge crystals will be pulled. - Silicon is a difficult fabric in order that huge wafers may be dealt with adequately. - Silicon is thermally sturdy as much as 1100°C in order that quite a few metallurgical operations (oxydation, diffusion, annealing ... ) could be accomplished adequately. - there's large quantity of silicon in the world in order that the bottom silicon wafer is reasonable. Unfortunatly, there are basic limits that can not be triumph over in silicon as a result of fabric houses: laser motion, infra-red detection, excessive mobility for example. the improvement of recent applied sciences of deposition and progress has opened new percentages for silicon established constructions. the well-known houses of silicon can now be prolonged and correctly utilized in combined constructions for components resembling opto-electronics, high-speed units. This has been pioneered by means of the mixing of a GaAs gentle emitting diode on a silicon dependent constitution via an MIT crew in 1985.
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Extra resources for Heterostructures on Silicon: One Step Further with Silicon
183, 1982, Jpn. Soc. of Appl. Phys. 9. : Hat. Res. Soc. Symp. 91, 149, 1987. 10. : Hat. Res. Soc. Symp. 116 (in press). 11. W. Matthews (Academic, New York, 1975), Part B, Chapter 8. 12. : Hat. Res. Soc. Symp. 116 (in press). 13. : J. Crystal Growth 85, 275, 1987. 14. Wessel, K. : Phil. Hag. A35, ~, 1523, 1977. 15. : Phil. Mag. A53, 1, 141, 1986. GROWTH OF GaAs and GaAlAs DOUBLE HETEROSTRUCTURES ON SILICON BY MOCVD R. K. RAO, B. SERMAGE, G. LEROUX, L. DUGRAND, N. DRAIDIA Centre National d'Eudes des Telecommunications Laboratoire de Bagneux 196 avenue Henri Ravera - 92220 BAGNEUX - FRANCE INTRODUCTION There has been a considerable interest in recent years on the heteroepitaxial growth of GaAs and its associated devices on silicon substrates.
Note the stacking faults on the (111) plane and cracking of the GaAs. 4. DISCUSSION The formation of threading dislocations and stacking faults in GaAs/Si heteroepitaxial growth can be caused by defect formation during growth and/or during cooling after the growth. During growth, the formation of misfit dislocations and their subsequent glide to the hetero-interface can result in threading dislocations in the epitaxial layer, as suggested by Matthews[ll). In GaAs/Si (211), these dislocations are type I or II.
2. CHARACTERIZATION The surface morphology of the layers has been examined by optical micrography and ALPHA step measurements. Since the surface roughness was found to increase with the thickness of the layer, the ratio of the roughness over layer thickness is taken as a measure of the smoothness of the layers. Double X-ray diffraction, photoluminescence measurement at 300K and 77K photoluminescence imaging and non radiative life time measurements have been performed. 27 Y. I. Nissim and E. ), Heterostructures on Silicon: One Step Further with Silicon, 27-36.